The use of virtual addressing is well known in the art of data processing. Conventionally, page tables are provided to maintain lists of virtual addresses with corresponding physical memory locations of the data associated with the virtual address, i.e. address translations. The process of obtaining a physical memory address of stored data from the page table list of virtual addresses is known as a page table walk.
It is common to use 4 Kb and 8 Kb virtual pages, but larger sizes, such as 2 Mb or 4 Mb or greater, can be used. Page table walks can take a significant amount of time compared to the operating speed of a processor. In order to avoid doing a page table walk to obtain each physical address of stored data corresponding to a virtual address, i.e. each translation, translation look-aside buffers (TLBs) are used to store address translations that are being used or may likely be used by a processor.
Conventionally, a processor will look first for a desired address translation in a TLB associated with a page table of a memory. If the desired address translation is found, the need to walk the page table is avoided. If the desired address translation is not found, the page table is walked to find the address translation. In some instances, multiple levels of TLBs that may serve different functions are disposed between the processor and the page table so that the processor will descend through the hierarchy of levels looking for a desired translation and perform a page table walk only if it is not discovered in descending through the hierarchy of TLBs.
Page tables and TLBs may generally be employed with any type of data processor, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), and an accelerated processing unit (APU).